1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to a cache controller operable to access data words during a linefill operation.
2. Description of the Prior Art
A cache may be arranged to store data and/or instructions so that they are subsequently readily accessible by a processor. Hereafter, the term “data word” will be used to refer to both instructions and data having any predetermined size. The cache will store a data word associated with a memory address until it is overwritten by a data word for a new memory address required by the processor. The data word is stored in cache using either physical or virtual memory addresses.
The processor will access the cache to determine whether a required data word is stored therein. Should the data word not be present in the cache then a so-called “cache-miss” will be issued which causes a read from a main memory. It will be appreciated that such a read from main memory is relatively slow compared to a read from the cache and can reduce the processing speed of the processor. It is known following a cache-miss to retrieve a number of logically adjacent data words from main memory. This is because it is recognised that most data word accesses are sequential and so it is likely that a subsequent access will also result in a cache-miss. By retrieving a number of data words from memory the likelihood of the required data word being present in the cache is increased. Such retrieval of data words is known as a so-called “linefill operation” whereby a complete cache line of, for example, eight data words will be fetched from main memory and stored into a single line of the cache.
It will be appreciated that the writing of data words to the cache is limited by the architecture provided. Typically, a linefill can take a number of clock cycles to complete. It is known to provide a linefill mechanism which receives the cache-miss and controls the retrieval of each data word from the main memory over the data buses to the cache. A known data bus may be arranged to retrieve data words in pairs from the main memory and, hence, may take four cycles to complete an example eight data word linefill.
It is known in such caches for each cache line to be provided with a valid flag which indicates whether the data words stored therein are valid and can be accessed. This valid flag is set once all the data words have been correctly retrieved from main memory and stored in the cache. Hence, the valid flag may not be set for a number of clock cycles, such as for example, four cycles.
It will be appreciated that it would be undesirable following a cache-miss for the processor to wait a number of cycles for the data word which caused the cache-miss to become accessible. Accordingly, it is known to provide a mechanism which routes the particular data word which caused the cache-miss to the processor whilst the linefill is taking place in order to improve performance.
However, as mentioned above, it is likely that a further data word being provided by the linefill will be needed by the processor before the linefill completes and the valid flag has been set indicating that the required data word is accessible.
Hence, a technique exists (as is described in our co-pending U.S. patent application 10/011,310, filed 11 Dec. 2001, now U.S. Pat. No. 6,782,482, the full disclosure of which is incorporated herein by reference) which enables data words being provided by the linefill to be accessed before the valid flag has been set. This technique utilises a so-called “fill buffer” in which the complete cache line is retrieved and stored in the linefill mechanism before providing the data words to the cache. It will be appreciated that the size of the bus between the linefill mechanism and memory could be selected to be any suitable size. Whilst the fill buffer enables each data word to be accessed during the linefill, the amount of logic gates required to implement the fill buffer is considerable. For example, a cache line which stores eight, 32-bit words would typically require at least 2,500 logic gates (assuming an eight word cache line which would require eight 32-bit registers with each register requiring 10 gates). It will be appreciated that it is desirable for cost and power consumption reasons to keep the amount of logic gates required to a minimum.
Accordingly, it is desired to provide a more efficient technique which enables data words being provided by a linefill to be accessed during a linefill.